5
Sync Input Leakage Current
SYNC = GND or V
IN
-
0.01
0.15
礎
Duty Cycle of External Clock Signal (Note 6)
20
-
80
%
PG_PWM
Rising Threshold
1mA source/sink
+5.5
8.0
+13
%
Falling Threshold
-11.5
-8.0
-5.5
%
LDO1 SPECIFICATIONS
Output Voltage
-
2.84
-
V
Output Voltage Accuracy
I
OUT
= 10mA
-1.5
-
1.5
%
Maximum Output Current (Note 6)
V
IN
= 3.6V
300
-
-
mA
Output Current Limit (Note 6)
330
770
-
mA
Dropout Voltage (Note 4)
I
OUT
= 300mA
-
125
200
mV
Line Regulation
V
IN
= 3.0V to 3.6V, I
OUT
= 10mA
-0.15
0.0
0.15
%/V
Load Regulation
I
OUT
= 10mA to 300mA
-0.5
0.2
1.0
%
Output Voltage Noise (Note 6)
10Hz < f < 100kHz, I
OUT
= 10mA
C
OUT
= 2.2礔
-
65
-
礦
RMS
C
OUT
= 10礔
-
60
-
礦
RMS
LDO2 SPECIFICATIONS
Output Voltage
-
2.84
-
V
Output Voltage Accuracy
I
OUT
= 10mA
-1.5
-
1.5
%
Maximum Output Current (Note 6)
V
IN
= 3.6V
200
-
-
mA
Output Current Limit (Note 6)
250
400
-
mA
Dropout Voltage (Note 4)
I
OUT
= 200mA
-
100
200
mV
Line Regulation
V
IN
= 3.0V to 3.6V, I
OUT
= 10mA
-0.15
0.0
0.15
%/V
Load Regulation
I
OUT
= 10mA to 200mA
-
0.2
1.0
%
Output Voltage Noise (Note 6)
10Hz < f < 100kHz, I
OUT
= 10mA
C
OUT
= 2.2礔
-
30
-
礦
RMS
C
OUT
= 10礔
-
20
-
礦
RMS
ENABLE (EN_PWM and (EN_LDO)
EN High Level Input Voltage
2.3
-
-
V
EN Low Level Input Voltage
-
-
1.0
V
RESET BLOCK SPECIFICATIONS
RESET Rising Threshold
2.68
2.79
2.81
V
RESET Falling Threshold
Sink 1.0mA/Source 0.5mA at 0.4V from GND/V
DD
2.7
2.77
2.79
V
RESET Threshold Hysteresis
-
20
-
mV
RESET Current Source
0.4
0.54
0.7
礎
RESET/RESET
Active Timeout Period (Note 5) C
T
= 0.01礔
25
-
-
ms
POWER GOOD (PG_LDO)
PGOOD Threshold (Rising)
+11
+15
+18
%
PGOOD Threshold (Falling)
-17
-15
-11
%
PGOOD Output Voltage Low
I
OL
= 1mA
-
-
0.5
V
Electrical Specifications Recommended operating conditions unless otherwise noted. V
IN
= V
IN
_LDO = PV
CC
= 3.3V, Compensation
Capacitors = 33nF for LDO1 and LDO2. T
A
= 25
o
C. (Note 2) (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISL6413